|About this Abstract
||2022 TMS Annual Meeting & Exhibition
||Electronic Packaging and Interconnections
||Low Temperature Solder Interconnect board level Shock Performance at elevated temperature
||Tae-Kyu Lee, Gnyaneshwar Ramakrishna, Young-Woo Lee, Edward Ibe, Karl Loh
|On-Site Speaker (Planned)
The adaptation of low melting temperature for solder interconnection comes with significant benefits to less warpage and component defect risk due to the lower assembly temperature, but counter with inferior shock performance due to less ductility in Sn-Bi eutectic alloy system. 12x12 mm chip array BGA (CABGA) components on 62mil think boards were shock tested at room temperature and elevated temperature with 1500G shock input. The shock performance between edgebond applied and no-edgebond shock is compared at room temperature condition and at 100oC environment. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron–backscattered diffraction (EBSD) imaging. The correlation between the shock induced straining at the solder joints, effect if the microalloy elements and the effect of the edgebond adhesive on the joint microstructure will be presented and discussed.
||Electronic Materials, Characterization, Mechanical Properties