The recent advances in semiconductor devices, such as reduced form factor, low power consumption with better performance, arises from advanced packaging technology by stacking multiple layers of integrated circuits. There are several methods and associated challenges with such packaging technology which result in low yields, such as alignment and bonding, managing stress induced warpage, etc. To overcome some of these challenges, surface preparation and managing the coating led warpage is critical. Here, we will present some process strategies to address both the challenges. The process optimization of coatings is aimed at minimizing the overall stress on the wafer by managing the temperature, thickness, layer selection among other parameters.