About this Abstract |
| Meeting |
2026 TMS Annual Meeting & Exhibition
|
| Symposium
|
Electronic Packaging and Interconnection Materials III
|
| Presentation Title |
Investigation of Silicon Wafer-Level Warpage under Varying Reflow Thermal Profiles, Wafer Sizes, and Thicknesses |
| Author(s) |
Muhammad Fikri Shamsuri, Mohd Zulkifly Abdullah, Mohd Sharizal Abdul Aziz |
| On-Site Speaker (Planned) |
Muhammad Fikri Shamsuri |
| Abstract Scope |
The continued miniaturization of electronic devices such as smartphones, tablets, sensors, and automotive systems has driven the adoption of advanced semiconductor packaging technologies. A critical challenge in wafer-level assembly is silicon wafer warpage, primarily caused by the coefficient of thermal expansion (CTE) mismatch between multi-layer materials. This warpage can significantly affect assembly yield and reliability by inducing defects such as delamination, solder joint fatigue, and thermal stress.
This study investigates silicon wafer-level warpage during reflow processes, focusing on the influence of reflow thermal profiles, wafer sizes, and thicknesses. Coupled solid mechanics and heat transfer simulations using ANSYS are employed to predict warpage behavior, with results validated through experimental measurements under controlled reflow conditions. The outcomes provide valuable insights for optimizing reflow profiles and package designs, offering practical guidance for minimizing warpage-induced defects and improving the reliability of wafer-level packaging. |
| Proceedings Inclusion? |
Planned: |
| Keywords |
Modeling and Simulation, Electronic Materials, Mechanical Properties |