Electronic Packaging and Interconnection: Poster Session
Sponsored by: TMS Functional Materials Division, TMS: Electronic Packaging and Interconnection Materials Committee
Program Organizers: Kazuhiro Nogita, University of Queensland; Mohd Arif Mohd Salleh, Universiti Malaysia Perlis; Dan Li, Beijing University of Technology; David Yan, San Jose State University; Fan-Yi Ouyang, National Tsing Hua University; Patrick Shamberger, Texas A&M University; Tae-Kyu Lee, Cisco Systems; Christopher Gourlay, Imperial College London; Albert T. Wu, National Central University

Monday 5:30 PM
March 20, 2023
Room: Exhibit Hall G
Location: SDCC

Session Chair: Kazuhiro Nogita, The University of Queensland; Chris Gourlay, Imperial College London


C-7: Dynamic Material Characterization through In-Situ Electrical Resistivity Measurements of High Temperature Transient Liquid Phase Sinter Alloys: Gilad Nave1; Patrick McCluskey1; 1University of Maryland
    As part of the effort to implement additive manufacturing techniques into the world of power electronics devices and materials that can operate at harsh environments, researchers and industry must mitigate multi-level challenges that span processing techniques, manufacturing scaling, manufacturing mobility, cost reduction, optimal material properties, and reliable material performance. This study presents a new method to dynamically test the electrical properties of a given solder alloy. The method is capable of testing the electrical properties from the moment in which the solder is pasty and mixed with multiple organics, to the point where the organics are evaporated and reacted, and the remaining material is only diffused metal powder. This new testing method allows to quantify multiple effects such as organic-metallic interactions, chemical effects, metallurgical effects, and in the context of additive manufacturing, this testing method provides a new design tool for faster processing, temperature profiles designs, and paste formulation design.

C-8: Low-temperature CMOS Compatible SLID & Eutectic Bonding for Wafer Level Packaging: Gürel Dimez1; Özgün Yurdakul1; Mertcan Sevinç1; Oğuzhan Temel1; Tayfun Akın1; Yunus Kalay1; 1Middle East Technical University
    Wafer-level packaging is crucial for the commercialization of MEMS devices. More than 50% of the production cost is related to packaging when device-level packaging is preferred. CMOS compatibility requires the process temperatures to remain below 450 ℃ while a minimum temperature of 400 ℃ is necessary for Ti getter film activation. In this study, we have investigated the properties of packages after AuSn & AuIn SLID bonded and AlGe eutectic bonded packages that can be used for wafer-level packaging above 400 ℃. In addition to binary systems, we also investigated the performance of AuInSn and CuInSn ternary SLID systems for hermetic packaging. SLID bonded samples yield shear strengths around 35 MPa while AlGe eutectic bonded samples have an average strength of 50 MPa. The Scanning Acoustic Microscopy analysis along with He-leak test results will be compared and discussed in detail.