Electronic Packaging and Interconnections 2021: Advanced Microelectronic Packaging Materials
Sponsored by: TMS Functional Materials Division, TMS: Electronic Packaging and Interconnection Materials Committee
Program Organizers: Mehran Maalekian, Materials & Metallurgy Expertise; Christopher Gourlay, Imperial College London; Babak Arfaei, Ford Motor Company; Praveen Kumar, Indian Institute of Science; Sai Vadlamani, Intel Corporation; Kazuhiro Nogita, University of Queensland; David Yan, San Jose State University

Wednesday 8:30 AM
March 17, 2021
Room: RM 22
Location: TMS2021 Virtual

Session Chair: Sai Vadlamani, Intel Corp.; Prithwish Chatterjee, Intel Corp.


8:30 AM  Invited
Advances in Low Temperature/Low Pressure Ag Sinter Joining and Its Thermal Performance: Katsuaki Suganuma1; Chuantong Chen1; Zheng Zhang1; Aiji Suetake1; Aya Iwaki1; Ming Hsieh1; Naoki Sato1; 1Osaka University
     Sinter joining with Ag particles has been recognized as one of the key interconnection technologies especially for power electronics applications. Ag reacts with oxygen to form nanostructure among particles and bulk surfaces resulting in excellent sintering capability at low temperature even blow 200 °C. There is no need to apply high temperature or high pressure to achieve bonding/wiring.One of the attractive features of Ag sinter joining is its thermal performance. The heat conductivity of a Ag layer sintered at 200 °C reaches about 200 W/m·K without any applied pressure. The transient thermal resistance of a sintered Ag die attach layer is below 0.05 cm2·K/W while that of high Pb solder is about 0.8 cm2·K/W. Thus Ag sinter joining can be applied not only to high performance die-attach but also to variety of heat dissipation interconnection materials.

8:50 AM  
Electric-enhanced Sintering of Copper Interconnects: Tzu-Hao Shen1; Albert T. Wu1; 1National Central University
    Due to the development of high power devices, Sn-based alloys are no longer suitable at severe conditions. Copper is a promising candidate for such applications for its high electromigration resistance, excellent electrical conductivity and mechanical properties. Sintering of Cu nanoparticles (CuNPs) is an attractive approach to fabricate joining materials at low temperature and the joints can sustain high-temperature operation. In this study, sintering is enhanced by applying electrical current to CuNPs. Different diameters of CuNPs are made as conductive ink. The ink is printed in V-grooves on Si substrates and pre-sintered at low temperature. Low current density is applied along samples at 150 oC for different durations to further sinter the CuNPs. The morphology and electrical behavior of the sintered CuNPs are studied. Electromigration of the sintered CuNPs is conducted when applying high current density. The results suggest electric-enhanced sintering of CuNPs can be a possible candidate for electronic devices.

9:10 AM  
Modeling and Simulation of Stress Gradient Driven Migration: Zachary Morgan1; Yongmei Jin1; Vahid Attari2; Raymundo Arroyave2; 1Michigan Technological University; 2Texas A&M University
    Stress gradients influence the migration velocity and path of defects such as voids and precipitates in solder interconnects. As physical size is reduced, the role of stress and its gradient on reliability become unclear due to the wide range of properties present in solder microstructures. In particular, anisotropy plays an increasingly important role in migration and deformation behavior. A phase field model is developed using microelasticity modeling to investigate the influence of stress concentrations on void and precipitate migration that accounts for driving forces for diffusion. Simulations reveal the influence of different loading conditions on defect migration and contribution of local variations in stress that give rise to internal stress gradients. Examples discussed include stress gradients caused by external loading and internal stress concentrations due to elastic property mismatches near grain boundaries, voids, and precipitates. These findings offer insight into the role of microstructure and stress on solder interconnect performance.

9:30 AM  
Plasticity and Contact Resistance Behavior in Wirebond Packaging: Allison Osmanson1; Mohsen Tajedini1; Hossein Madanipour1; Yi Ram Kim1; Choong-Un Kim1; 1University of Texas at Arlington
    The mechanism behind contact area, geometry, and properties of wirebonds in electronic packaging was investigated in this study. This research is spurred by our recent findings suggesting an unexpected sensitivity to seemingly minor changes in the wirebond parameters such as the pad thickness. The trends observed indicate that thicker aluminum pads, shorter wire lengths, and thicker wire diameters yielded lower contact resistances. The reduction in the contact resistance is much more than what is expected from a simple change in the wire geometry, indicating the presence of a mechanism behind the contact resistance to change disproportionally with the change in wire or bond geometry, indicating that residual stress, yield strength, and the work hardening rate affects the plasticity of the wirebond. Applications of this theory can provide valuable insight that can be cultivated by the packaging industry. The details of this study will be discussed in length in this report.

9:50 AM  
The Effects of DC, Pulsed DC, and AC Load Conditions on Electromigration Failure Mechanism in Solder Interconnects: Yi Ram Kim1; Hossein Madanipour1; Allison Osmanson1; Mohsen Tajedini1; Choong-Un Kim1; Patrick Thompson2; Qiao Chen2; 1University of Texas at Arlington; 2Texas Instruments, Inc.
    The effects of various current load conditions on electromigration (EM) mechanisms are investigated in this study. The lead-free Sn-Ag-Cu (SAC) alloy solder interconnects in Wafer-level Chip Scale Package (WCSP or WLSCP) are undergone accelerated EM testing with high temperature and high current densities. For comparative studies, samples are tested under various current load conditions, including pulsed direct current (DC), DC, and alternating current (AC) loads. The previously reported results indicate that pulsed DC has two competing factors that accelerate and decelerate the EM failure rate depend on duty factor. The effects of the AC load on the EM mechanism are investigated and compared to DC and pulsed DC load conditions to find any unexpected failure mechanism. We expect to have slower failure rates but similar failure mechanism to DC load, such as runaway failure. The details of the findings will be discussed in this report.

10:10 AM  
Sintered Micro-silver Joints with the Addition of Indium Applied to Power IC Packaging: Chin-Hao Tsai1; Wei-Chen Huang1; Ly May Chew2; Wolfgang Schmitt2; Hiroshi Nishikawa3; C. Robert Kao1; 1National Taiwan University; 2Heraeus Deutschland GmbH & Co. KG; 3Joining and Welding Research Institute, Osaka University
    Over the past decades, the demand for high temperature power electronics soars rapidly. Due to its high power density, the operating temperature of high power devices increases, which might lead to failure of conventional low temperature tin-based packaging materials. As a result, new packaging material is needed for die attachment technology of power electronic components. In this research, silver paste composed of micro-scale particles is utilized for transient liquid phase sintering with indium foil. The purpose of adding indium to sintered micro-silver joints is to enhance the mechanical property and improve high temperature reliability. Shear tests and thermal aging tests are conducted to investigate characteristics of sintered Ag and Ag-In joints. It is concluded that Ag-In intermetallic compounds exhibit excellent mechanical property and oxidation resistance property.

10:30 AM  
Low-Temperature and Pressureless Cu-to-Cu Bonding by Electroless Pd Plating Using Microfluidic System: Po Shao Shih1; Zhen De Ma1; Han Tang Hung1; Jeng Hau Huang1; C.Robert Kao1; 1National Taiwan University
    Fulfilling the packaging trend of getting lighter weight and possessing multi-functional modulus simultaneously, 3D-IC technology has implemented of finer pitch and higher interconnect density over the past decades. Thermocompression bonding, which is a promising technique for high-density integration and has been applied widely among industries, might not be the best choice for devices which cannot withstand the high temperature and pressure during the bonding process. To overcome this challenge, a novel Cu-to-Cu bonding process using electroless Palladium plating in an airtight microfluidic system around 70℃ was investigated. This method provides a low temperature and pressureless operating environment and full-metal interconnections after bonding. The bonded pillars were analyzed by scanning electron microscope. In addition, the cross-section images and the plating condition were further confirmed and investigated by focused ion beam and electron probe micro-analyzer. This innovative method might be a potential candidate for future low stress and low thermal budget bonding.