Electronic Packaging and Interconnection: Quality and Reliability of Advanced Microelectronic Packaging
Sponsored by: TMS Functional Materials Division, TMS: Electronic Packaging and Interconnection Materials Committee
Program Organizers: Kazuhiro Nogita, University of Queensland; Mohd Arif Mohd Salleh, Universiti Malaysia Perlis; Dan Li, Beijing University of Technology; David Yan, San Jose State University; Fan-Yi Ouyang, National Tsing Hua University; Patrick Shamberger, Texas A&M University; Tae-Kyu Lee, Cisco Systems; Christopher Gourlay, Imperial College London; Albert T. Wu, National Central University
Monday 8:30 AM
March 20, 2023
Room: Sapphire D
Location: Hilton
Session Chair: Tae-Kyu Lee, Cisco Systems; Kazuhiro Nogita, The University of Queensland
8:30 AM Introductory Comments
8:40 AM Invited
Power Cycling Reliability with Temperature Deviation of Pressureless Silver Sinter Joint for Silicon Carbide Power Module: Won Sik Hong1; Mi Song Kim1; 1Korea Electronics Technology Institute
We developed silver (Ag) sintered power module with no pressure for electric vehicle. Silicon carbide (SiC) MOSFET device was sintered on Ag finish silicon nitride (Si3N4) active metal brazed (AMB) ceramic substrate with Ag paste under 240 ℃, 75 min in vacuum and nitrogen gas atmosphere. To verify the sinter joint reliability, we conducted 2 kinds of power cycling tests (50-100 ℃ (△Tc=50℃) and 50-150 ℃ (△Tc=100℃), 3000 cycles), and then, on resistance and switching efficiency of the power module were compared. Based on these results, we confirmed the reliability and electrical performance of the Ag sintered power module.
9:05 AM
Investigation of Corrosion for Ni-based Surface Finish: Jui-Lin Chao1; Si-Wei Lin1; Jing-Chie Lin1; Yi-Hung Liu1; Chih-Yuan Hsiao2; Freeze Wang2; Nico Li2; Alber T Wu1; 1National Central University; 2Taiwan Uyemura Co Ltd., 337 Taiwan
Electroless, electroplated Ni-based single layer and multilayer Ni/Pd/Au are used as the surface finishing materials deposited on ceramic substrates that can be applied to high-power devices. Electrochemical impedance spectroscopy and polarization curves analysis were adopted to investigate the corrosion behavior. The corrosion potential and current are used to discuss the corrosion mechanism. When the samples were placed in a chamber with various SO2 concentrations, better corrosion resistance was observed for single-layer electroless Ni and multilayer electroplated Ni/Pd/Au compared with that for their well-crystalline electroplated and electroless counterparts, respectively. EBSD results showed that galvanically displaced Pd(P) and immersion Au provided numerous diffusion paths for growing the corrosion products on the electroless Ni/Pd/Au surface than on the electroplated surface due to a high grain boundary density. These results prove that the microstructure and crystallinity of the surface finishing layers have an important effect on corrosion behaviors.
9:25 AM
Mitigation of Tin Whiskers Growth by Co-electroplating Sb: Lei Zhang1; Xia Wang1; Hongwei Qu1; 1Oakland University
Electroplating Sn coatings are used extensively in electronics industry because of its excellent solderability, ductility, electrical conductivity, and corrosion resistance. However, tin whiskers have been observed to grow spontaneously from the electroplating tin coatings, which can lead to short circuits and devices failures. This problem was solved in the past by adding a few percent of Pb until Pb is banned under ROHS-WEEE restrictions in 2006. In this study, we have developed a state-of-the-art aqueous electroplating bath formulation to deposit a Sn60Sb40 alloy. The alloying of Sn with Sb was observed as effective in suppressing the metallic whisker formations from electroplated Sn-Sb surface finishes under externally applied mechanical stress. The microstructure characterization and the physics behind the whisker mitigation mechanism due to Sb alloying was explored using SEM, EBSD and XRD techniques.
9:45 AM Break
10:05 AM
Low Melting Temperature Solder Interconnect Thermo-mechanical Performance Enhancement Using Elemental Tuning: Tae-Kyu Lee1; Nilesh Badwe2; Greg Baty3; Raiyo Aspandiar4; Young-Woo Lee5; 1Cisco Systems; 2IIT Kanpur; 3Portland State University; 4Intel; 5MK Electron
Recent studies on Sn-Bi based low melting temperature solder interconnect with minor elemental tuning show relatively good thermal cycling performances compared to conventional Sn-Ag-Cu based solder interconnects at a given thermal cycling profile. The degradation mechanism is related to twin boundary formation, a different mechanism compared to general Sn-Ag-Cu solder interconnects. An attempt to slow down the degradation rate is implemented with adding Indium into the eutectic Sn-Bi based alloy system. Along with the thermal cycling performance enhancement, the mechanical shock performance is also investigated. In this study, 12x12 mm chip array BGA (CABGA) components on 62mil think boards were thermal cycled with -40 to 100oC profile and 10min dwell for thermal cycling and 1500G was applied for mechanical shock. The correlation between crack initiation, crack propagation, sub-grain development and localized recrystallization were compared using polarized imaging and Electron–backscattered diffraction (EBSD) imaging.
10:25 AM
Probing Defect Formation and Reliability of Solder Interconnects Produced through Quasi-ambient Bonding: Wajira Mirihanage1; Saranarayanan Ramachandran1; Zhaoxia Zhou2; Zhe Cai1; Fan Wu1; Canyu Liu2; Han Jiang2; Christoforos Panteli3; Stuart Robertson2; Andrew Holmes3; Sarah Haigh1; Changqing Liu2; 1The University of Manchester; 2Loughborough University; 3Imperial College London
High-temperature electronics with wide bandgap semiconductors demand reduced bonding time and temperatures to maximise interconnect reliability. Quasi-ambient bonding (QAB) with reactive nanofoils provides instantaneous localised heating right at the bond interfaces and can be a viable solution. Reactive nanofoils are laminated multilayer materials with large negative enthalpy of mixing. The heating occurs as a small burst of energy at fast propagation velocities. However, very limited details are known about the interaction of the reactive nanofoil with solders, solidification and defect formation. High energy synchrotron X-rays were used as a tool to examine the QAB interconnect formation and the reliability. Real time X-radiography images reveal the dynamic nature of the melting and solidification. The defective pore formation was found to correlate with the solidification time and thermal properties. Distributions of residual stress throughout die-attach interconnects were mapped using X-ray diffraction and analysed to understand the bond reliability.
10:45 AM
The Effect of Grain Boundary Type on Void Formation in a Through Silicon Via (TSV): Armin Shashaani1; Panthea Sepehrband1; 1Santa Clara University
In the 3D IC packaging technology, to achieve mechanical and electrical interconnection in the vertical direction, the chips are stacked by through-silicon-vias (TSV). As the fundamental structure of 3D IC packaging, TSV reliability plays a critical role in the service life of the chip. Void nucleation is considered the initial phase of various failure mechanisms in TSVs. Void nucleation is a complex process to study experimentally and there are conflicting views on the impact of crystallographic textures on void formation. To systematically study the effect of texture and to detect the initial phase of void nucleation, in-situ analysis of atomic arrangement is specifically designed bicrystals of copper (the main material of TSV) is conducted through Molecular Dynamics (MD) simulations. The effect of grain orientations and grain boundary characteristics on vacancy diffusion, which leads to void nucleation, is investigated, and the preferred crystallographic configurations for delaying void formation are defined.
11:05 AM
Phase-field Modeling of Electromigration-mediated Void Migration and Coalescence under Mechanical Compression: William Farmer1; Kumar Ankit1; 1Arizona State University
Electromigration (EM) occurs due to momentum transfer between the metallic ions of the interconnect and the electrons, which drift in the direction of the externally applied electric field. EM-induced defects can manifest as nucleation and growth of micro-voids and hillocks, grain boundary (GB) slits, and metallization, which lead to failure of interconnects and soldered joints. To gain an understanding of interconnect failure mechanisms, we develop a phase-field model, which encapsulates the physics of vacancy diffusion, to simulate the morphological evolution of voids under different operating conditions. Our simulations display the effects of elastic inhomogeneity, current densities, and back stress on the migration and coalescence of voids. Based on an in-depth parametric study, inferences are drawn to formulate strategies for which the void migration in interconnects can be suppressed.