2017 Symposium on Functional Nanomaterials: Emerging Nanomaterials and Nanotechnology: Nanomaterials for Nanoelectronics
Sponsored by: TMS Functional Materials Division, TMS: Nanomaterials Committee
Program Organizers: Jiyoung Kim, University of Texas; Stephen McDonnell, University of Virginia; Chang-Yong Nam, Brookhaven National Laboratory; V. U. Unnikrishnan, The University of Alabama; Nitin Chopra, The University of Alabama

Tuesday 2:00 PM
February 28, 2017
Room: Pacific 26
Location: Marriott Marquis Hotel

Session Chair: Nitin Chopra, University of Alabama; JangSik Lee, Pohang Institute of Sci. & Tech.


2:00 PM  Invited
Recent Advancement in Graphene-based Layer Transfer: Jeehwan Kim1; 1Massachusetts Institute of Technology
    As a strategy to save the cost of expensive substrates in semiconductor processing, the technique called “layer-transfer” has been developed. In order to achieve real cost-reduction via the “layer-transfer”, the following needs to be insured: (1) Reusability of the expensive substrate, (2) Minimal substrate refurbishment step after the layer release, (3) Fast release rate, and (4) Precise control of a released interface. Although a number of layer transfer methods have been developed including chemical lift-off, optical lift-off, and mechanical lift-off, none of those three methods fully satisfies conditions listed above. In this talk, we will discuss our recent development in a “graphene-based layer-transfer” process that could fully satisfy the above requirements, where epitaxial graphene can serve as a universal seed layer to grow singlecrystalline III-N, III-V, II-VI and IV semiconductor films and a release layer that allows precise and repeatable release at the graphene surface.

2:30 PM  Invited
Van Der Waals Epitaxy of TMDs and Topological Insulators: R. Yue1; L. A. Walsh1; A. T. Barton1; Y. Nie1; H. Zhu1; D. Barrera1; S. McDonnell2; R. Addou1; Q. Wang1; N. Liu1; M. J. Kim1; J. Hsu1; K. Cho1; Y. J. Chabal1; J. Kim1; R. M. Wallace1; L. Colombo3; Christopher Hinkle1; 1University of Texas at Dallas; 2University of Virginia; 3Texas Instruments
    In this work, we demonstrate the high-quality MBE heterostructure growth of various layered 2D materials by van der Waals epitaxy (VDWE). The coupling of different types of van der Waals materials including transition metal dichalcogenide thin films (e.g., WSe2, WTe2, HfSe2) and topological insulators (e.g., Bi2Se3) allows for the fabrication of novel electronic devices that take advantage of unique quantum confinement and spin-based characteristics. We demonstrate how the van der Waals interactions allow for heteroepitaxy of significantly lattice-mismatched materials without strain or misfit dislocations. Yet, at the same time, the VDW interactions are strong enough to cause rotational alignment between the epi-layer and the substrate, which plays a key role in the formation of grain boundaries. To enhance larger area 2D growth, the complex interactions related to nucleation and growth were investigated resulting in grain sizes an order of magnitude larger than other reported MBE grown 2D materials.

3:00 PM  
Design of 2-D Vertical Heterostructures for Steep-slope Devices: Philip Campbell1; Jake Smith1; Jud Ready2; Eric Vogel1; 1Georgia Institute of Technology; 2Georgia Tech Research Institute
    As a result of aggressive device scaling, the MOSFET architecture is approaching several limitations which require exploration of alternative devices. One specific device which has attracted significant attention is the two-dimensional tunnel field-effect transistor (2D-TFET), composed of a pair of two-dimensional semiconductors separated by an insulating layer. Top and bottom gates control the band alignment by modulating the carrier concentration in the respective layer. Steep-slope operation in the 2D-TFET depends on achieving alignment between the conduction band of one layer and the valence band of the other layer. This work explores the potential for steep-slope behavior in the MoS2-WSe2 system. Further, the relationship between device performance and several material or device parameters, such as gate work functions, doping, lattice constant mismatch between the 2D materials, and bias voltages are explored to understand how device performance can be tuned for specific applications.

3:20 PM  Invited
Silicate Thin Films with Aligned Nanochannels by Surfactant Mediated Sol-gel Approach: Mechanism and Limitations: Choong-un Kim1; 1University of Texas at Arlington
    Silicate based thin films with density array nanochannels have been a subject of intense studies in recent years as they can be used as a template for various functional devices. Among various possible approaches, a surfactant mediated film growth is known to be the fully realized. This method involves deposition of silicate-surfactant-micelle and applies an external forces for assembly of micelle in desired direction. What is not well known, however, is the fact that this approach is with fundamental limitations that inhibit the perfect alignment of the micelle; the interplay between the configuration entropy, electrostatic field, and surface energy results in partial alignment, and such limitations are not practically possible to overcome. This paper presents thermodynamic force-balance consideration of the interaction between the micelle size, substrate and air and discuss the mechanism behind the inhibition of channel alignment.

3:50 PM Break

4:10 PM  Invited
Redefining Energy-efficient Systems via a Unified Memory Subsystem in STT-MRAMy: Seung Kang1; 1Qualcomm Technologies, Inc.
    Today, technology innovations are driven largely by applications and the ecosystems around them. Emerging applications such as Internet-of-Things (IOT), wearables, and bioelectronics integrated circuits demand innovative systems that maximize energy efficiency. These devices need to be always-on, always-aware, and always-connected, despite the fact that their active duty cycles are low. Limited by intrinsic memory attributes, conventional systems rely both on a nonvolatile storage and on a volatile working memory simultaneously. A unified memory subsystem, built on embedded STT-MRAM which combines these two types of memories, can eliminate unnecessary energy-hungry transactions and improve the system energy efficiency dramatically. This talk overviews recent advances and prospects of STT-MRAM by focusing on materials and devices from the perspective of energy efficiency and scaling.

4:40 PM  
Protein-based Resistive Switching Memory with Configurable Switching Properties: Sungjo Kim1; Jang-Sik Lee1; 1Postech
    Resistive switching memory (ReRAM) based on natural materials has received great attention as emerging memory devices due to flexible, low cost, biocompatible, and biodegradable properties. Among them, proteins show the feasibility for ReRAM application because of their good resistance switching properties. Nowadays, proteins embedding metal nanoparticles (NPs) have been reported to show improved resistive switching characteristics by formation of charge trapping sites. Here, we investigate configurable resistive switching behaviors based on interaction between albumen proteins and Au NPs. According to the degree of agglomeration of Au NPs in albumen, reversible to irreversible resistive switching is observed. By controlling the agglomeration of Au NPs in albumen it is possible to control the switching behaviors in protein-based ReRAM. Detailed device fabrication and electrical characterization with an emphasis on the interaction between albumen and Au NPs will be presented.

5:00 PM  
Enhancement-mode ALD DEZ-H2O-treated InGaAs MOSFETs with High-k Gate Dielectric: Jae-Gil Lee1; Young-Chul Byun1; Dushyant Narayan1; Jiyoung Kim1; 1The University of Texas at Dallas
    We have fabricated enhancement-mode In0.53Ga0.47As n-channel MOSFETs with high-k HfZrO2 gate dielectric. Passivating the surface of InGaAs is important for realizing high performance devices since there could be defects at the oxide/InGaAs interface. A 10 % ammonium sulfide and an in-situ ALD DEZ-H2O treatment were carried out before gate oxide deposition, which dramatically improves the interface quality between a gate oxide and InGaAs. The fabricated MOS capacitors and transistors were measured at low temperatures from 100K to 273K. At low temperatures, less than 200K, the subthreshold slope and the off-state current in current-voltage characteristics were decreased due to a trap response freeze out, as compared to room temperature. Low frequency dispersion, an on/off ratio of ~106, a threshold voltage of 2 V, and an extracted electron mobility of 930 cm2/V-s were achieved when measured at 100K. Acknowledgment (Grant No. 10045216 funded through KEIT by MOTIE and COSAR in Korea)

5:20 PM  
Improvement of Interface Properties on High Mobility Substrates by Low Temperature (100 C) Deposited-ZrO2: Young-Chul Byun1; Jae-Gil Lee1; Joy Lee1; Jiyoung Kim1; 1The University of Texas at Dallas
    Low-temperature atomic layer deposition (LT-ALD) processes have generated immense interest due to their widespread application in polymers, organic materials, flexible electronics, and back-end of the line (BEOL) processes for electronic materials. In this study, LT (100 C) ZrO2 deposited using TDMAZr and O3 is systematically studied on Si, InGaAs, and GaN substrates. On In0.53Ga0.47As, reduction of accumulation frequency dispersion is achieved using LT-ZrO2 films. Additionally, LT-ZrO2 films on GaN recessed gate high electron mobility transistors (HEMT) demonstrate a lower leakage current and improved interface state density and hysteresis from C-V measurements compared to the high-temperature deposition process. This phenomenon is due to the minimization of the interfacial layer formation, which suppresses film crystallization. On III-V and III-N substrates, the reduction in the ALD process temperature results in improvements of electronic properties. This work was supported by the Grant No. 10045216 and 10048933 funded through by the MOTIE/KEIT.