| Organizer(s) |
Eric J. Cotts, Binghamton University
David Yan , San Jose State University
Mike Wolverton, Raytheon Space and Airborne Systems
Iver Anderson, Ames Laboratory
HongWen Zhang, Indium Corporation
Bhaskar Majumdar, New Mexico Tech
Nilesh Badwe, Intel Corporation
Albert Wu, National Central University |
| Scope |
Continued advances in technology are required to package thinner devices which operate at higher bandwidths and lower powers. Warpage, thermal management, thermal expansion mismatches, three dimensional structure and efficiency challenges must be addressed. As the state of the art becomes smaller and includes new embedded packaging technologies, plastic and hybrid electronics, and additive manufacturing/3D printing, new roadblocks arise. This workshop will address new demands on interconnects and packaging at all levels, including alternative interconnects, conductive adhesive, Pb free solder, epoxy, substrates, 3D packaging, wafer level packing, quality, reliability, and failure analysis. |