| Abstract Scope |
AlGaN/GaN High Electron Mobility Transistors (HEMTs) have garnered a great deal of interest due to their high performance capabilities. As this technology has become a key component for high frequency and high power applications, the need to understand the degradation mechanisms that affect the long-term reliability has become increasingly important. High power operation requires the use of large voltages, which in turn results in considerable electric fields in the device. Previous studies have shown an electric field driven degradation mechanism under high reverse gate bias. Under high reverse gate bias, gate leakage current in AlGaN/GaN HEMTs is seen to steadily increase. Once a critical voltage (VCRI) is reached, the gate leakage currents increase by up to several orders of magnitude. This sharp rise in current has been attributed to the inverse piezoelectric effect. High reverse gate bias step-stress from -10 V to -42 V on AlGaN/GaN HEMTs were performed and resulted in an increase in gate leakage current about 5 orders of magnitude, with a sharp one order of magnitude increase in current at the critical voltage. Numerous devices were step-stressed at temperatures ranging from 25 °C to 150 °C. During elevated temperature stress tests, AlGaN/GaN HEMTs were found to exhibit a negative temperature dependence of the critical voltage (VCRI) for irreversible device degradation to occur during bias-stressing. VCRI follows a log relationship of the form VCRI=V0exp(-Ea/kT) where the activation energy is 38 meV and the value for V0 is around -28 V at room temperature in our devices.Though the stress temperatures were well below reported thermal instability for Ni/Au on AlGaN, previous research has shown consumption of a native oxide layer between the Schottky contact and AlGaN layer after high reverse gate bias stress at room temperature. At elevated temperatures, devices exhibited similar gate leakage currents before and after biasing to VCRI, independent of both stress temperature and critical voltage, indicating a current-driven degradation mechanism. Gate and drain lag measurements were also performed of devices stressed at elevated temperatures in order to further investigate the role of shallow and deep traps. For devices stressed at 40 °C, gate lag increased five times the original value of fresh devices while drain lag increased by more than twice the unstressed value. As stress temperature increased to 150 °C, gate and drain lag show an exponential decay. |