Future downscaling of metal-oxide-semiconductor (MOS) devices relies on the successful introduction of high-k dielectrics and metal electrodes, which will replace the traditional poly-Si/SiO<SUB>2</SUB> gate-stack. Gd<SUB>2</SUB>O<SUB>3</SUB> is one of the only materials that have been reported to suit the industry’s requirements for 2016. In addition, Gd<SUB>2</SUB>O<SUB>3</SUB> has a low lattice mismatch to Si, which enables the growth of a single-crystalline oxide layer. Additional structures can be obtained by controlling the oxide growth temperature and substrate orientation.
The aim of this research is to study the effect of oxide structure on the electrical properties of metal/Gd<SUB>2</SUB>O<SUB>3</SUB>/Si gate stacks. Electrical properties were studied by examining MOS capacitors with either Pt or Ta as the metal gates.
Three different structures of Gd<SUB>2</SUB>O<SUB>3</SUB> were deposited by molecular-beam epitaxy (MBE). Amorphous layers were deposited at 90°C, while layers deposited at 600°C were crystalline, and their morphology was observed to depend on the Si orientation. Single-crystalline layers were obtained on Si(111), whereas on Si(100), domain-structured layers were obtained. In the case of domain-structured Gd<SUB>2</SUB>O<SUB>3</SUB>, a silicate-like interfacial layer was observed at the oxide/Si contact. Electrical measurements revealed that the k-value of this interfacial layer is lower than that of the oxide itself.
The electrical properties of Gd<SUB>2</SUB>O<SUB>3</SUB> were observed to be almost independent of the oxide structure. The oxide k-value was similar for all structures, however, the k-value of domain-structured Gd<SUB>2</SUB>O<SUB>3</SUB> (17.7± 0.8) was somewhat higher than those of single-crystalline (16.3± 0.7) and amorphous (16.9± 0.8) layers. The electron effective mass in crystalline Gd<SUB>2</SUB>O<SUB>3</SUB> was found to be (0.1± 0.02)•me, while for amorphous layers, a value of (0.5± 0.1)•me was obtained. The conduction mechanism through crystalline Gd<SUB>2</SUB>O<SUB>3</SUB> was found to be contact-limited in most of the measured conditions; with a barrier height of (0.6± 0.1) eV at Pt/Gd<SUB>2</SUB>O<SUB>3</SUB> interfaces. This value is explained by the existence of a defect-related energy band in the oxide.
In contrast to the oxide properties, the extent of Fermi-level pinning at metal/Gd<SUB>2</SUB>O<SUB>3</SUB> interfaces was found to be significantly affected by the oxide structure. At metal/single-crystalline Gd<SUB>2</SUB>O<SUB>3</SUB> interfaces, Fermi-level pinning was negligible, while at metal/amorphous Gd<SUB>2</SUB>O<SUB>3</SUB> interfaces, a dominant pinning effect could be observed. These results are explained in terms of the metal-induced gap states model.