|About this Abstract
||2017 TMS Annual Meeting & Exhibition
||Emerging Interconnect and Pb-free Materials for Advanced Packaging Technology
||Influence of Annealing Conditions on the Microstructure of Cu-filled Through-silicon Vias
||Zhao Xuewei, Limin Ma, Fu Guo
|On-Site Speaker (Planned)
Reliability investigation is a key link in the industrialization of through-silicon via(TSV) technology. One issue of great concern for TSV reliability is the coefficient of thermal expansion(CTE) mismatch between different materials in TSV structures. The CTE mismatch may induce thermal stresses at interfacial region when TSVs experience temperature changes during the processes of manufacture and application. These stresses may affect negatively the performance of production, and possibly lead to failure. By annealing, microstructure changes of TSVs can be investigated and analyzed to explain and optimize the thermo-mechanical behaviors of TSV structures. In this paper, microstructure changes of Cu-TSV samples under different test conditions are observed by FIB-SEM and EBSD method, influences of the temperature and heating rate on microstructure evolution and defect formation are analyzed and compared systematically. Voids in copper, cracks in the interface and intrusion of copper have been observed, and the correlated mechanism will be discussed.
||Planned: Supplemental Proceedings volume