| About this Abstract |
| Meeting |
2011 Electronic Materials Conference
|
| Symposium
|
2011 Electronic Materials Conference
|
| Presentation Title |
LL10, 3C-Silicon Carbide Epitaxy by Means of Silicon Carbide-on-Silicon Wafer Bonding |
| Author(s) |
Michael Robert Jennings, Tony Rogers, Amador Pérez-Tomas, Nick Aitken, Peter Ward, Andrea Severino, Craig Fisher, Peter Gammon, Philip Mawby |
| On-Site Speaker (Planned) |
Michael Robert Jennings |
| Abstract Scope |
Silicon Carbide (SiC) is widely accepted to be the material of choice for the next generation of power semiconductor devices, due to its superior material properties such has high critical electric field strength, high thermal conductivity and low intrinsic carrier concentration at room temperature. Although Cree inc. have recently commercialised a SiC power MOSFET, there are still key technological drawbacks associated with this device that are hampering its widespread uptake. The cubic form of SiC has many advantageous properties that should allow an increased MOSFET channel mobility and simplified processing with respect to its 4H-SiC counterpart. In this paper, we present a novel wafer bonding technique in an attempt to overcome the wafer bowing problem of 3C-SiC growth on silicon (Si). This involves the fabrication of wafer bonded polycrystalline SiC wafers onto crystalline Si <111> wafers. Wafer bonding was performed on polycrystalline 4” SiC (poly-SiC) carriers supplied by PocoGraphite. The fabrication of the SiC carrier wafers is based on utilising graphite as a precursor. The wafer is then machined from this graphite material, purified and subjected to a proprietary process that converts the graphite to high purity polycrystalline SiC. In order to achieve an acceptable bond, the poly-SiC carrier wafers were polished at NovaSiC. This is the first time a polishing process has been attempted on such polycrystalline SiC carrier wafers. It is presumed that for high quality wafer bonding to be successful, a root mean square (rms) roughness of less that 0.5 nm is required. Due to the novel nature of the poly-SiC carrier wafer polishing process, this proved to be difficult. Atomic force microscopy (AFM), total thickness variation (TTV) and bearing area ratio calculations were performed by Applied Microengineering Limited (AML). Here we consider the two smoothest poly-SiC carrier wafers, coined poly-SiC wafers 1 and 2. Poly-SiC carrier wafers 1 and 2 revealed rms roughness values of 3.96 and 8.24 nm respectively. A typical Si wafer rms roughness was ~0.3 nm. The total thickness variation (TTV) for both wafers was in the range of 60-80 µm. The predicted Abbott-Firestone curve based primarily on the rms roughness of the wafers to be bonded was calculated. Bearing ratios of 0.3% and 0.05% at a depth of 1.4 nm were calculated for wafers 1 and 2 respectively. The process for bonding the Si to poly-SiC carrier was as follows; firstly the wafers were subjected to a SC1 (NH<SUB>4</SUB>OH : H<SUB>2</SUB>O<SUB>2</SUB> : DI water) chemical clean followed by an in-situ plasma clean in an oxygen ambient for the purpose of activating the bonds. Secondly the wafers were mechanically bonded at room temperature and thirdly, the bonded wafers were annealed at 500 °C for sufficient bond strengthening to occur. |
| Proceedings Inclusion? |
Undecided |