GaN HEMTs are continuously showing their impressive potential for RF and power switching application. Nevertheless their reliability still needs to be investigated in order to use them in commercial and military applications. Several authors have reported performance degradation both in the dynamic and static characteristics [1,2,3,4] of GaN HEMTs due to the formation of trap states [1,4] within the AlGaN barrier layer when high electric fields are applied to the gate-drain device junction. In this work we discuss how trap state formation during reverse gate-source and gate-drain step-stress tests can affect device static characteristics, and show through numerical simulations how the observed degradation can be explained by means of localized defects at the gate-source or gate-drain edge in the AlGaN barrier. The devices tested were GaN HEMT grown on SiC substrates with a total gate periphery of 4x25μm and a 0.3μm gate length. Part of the devices tested were step-stressed by applying a negative gate-drain voltage of -2.5V/step for a total time of 5 minutes with the source terminal left open, while other devices were step-stressed by applying a negative gate-source voltage of -2.5V/step for a total time of 5 minutes with the drain terminal left open. In both cases device static I-V characteristics remained unchanged up to reverse voltage of approximately 25V after which a significant increase in reverse current as well as a decrease in DC current levels were observed. Gate-drain stressed devices showed an increase in output conductance as well as a softening of the knee-voltage while gate-source stressed ones showed a reduction of DC current levels in the I-V characteristics whose still showed a sharp knee and a low output conductance. Numerical Simulations carried out by means of the commercial DESSIS-ISE (Synopsis Inc.) simulator showed that acceptor traps placed at 0.5eV from the conduction band at the gate-drain or the gate-source edge within the AlGaN barrier can qualitatively explain the observed different devices degradation when applying gate-drain or gate-source high electric fields.  Joh Jungwoo et al., “Impact of Electrical Degradation on Trapping characteristics of GaN High Electron Mobility Transistors”, IEEE IEDM 2008, Dec. 2008.  A. Chini et al., “Correlation between DC and rf degradation due to deep levels in AlGaN/GaN HEMTs”, IEEE IEDM 2009, Dec. 2009.  E. Zanoni et al., “Localized damage in AlGaN/GaN HEMTs induced by reverse bias testing”, IEEE Electron Device Letters, May 2009.  A. Chini et al., “Evaluation of GaN HEMT degradation by means of pulsed I-V, leakage and DLTS measurements”, IET Electronics Letters, Apr. 2009.