| Abstract Scope |
Recent N-polar AlGaN/GaN MIS-HEMTs, using High Temperature CVD (HTCVD) grown Si<SUB>x</SUB>N<SUB>y</SUB> as the gate insulator, have demonstrated small-signal and large-signal performances comparable to Ga-polar devices. A recessed gate structure with integrated slant field plates, obtained by a timed etch through the PECVD Si<SUB>x</SUB>N<SUB>y</SUB> passivation, is normally used to prevent DC to RF dispersion in these devices. However, such a timed gate recess etch is very unreliable due to poor selectivity between PECVD Si<SUB>x</SUB>N<SUB>y</SUB> used for surface passivation, and HTCVD Si<SUB>x</SUB>N<SUB>y</SUB> used as the gate dielectric. This leads to either a high gate leakage (for over-etching), or a low transconductance (for under-etching). Despite these issues, HTCVD Si<SUB>x</SUB>N<SUB>y</SUB> is still preferable over other gate dielectrics, because it is a more mature technology and it can be deposited in-situ in MOCVD chamber. This work presents an Al<SUB>2</SUB>O<SUB>3</SUB> based etch-stop technology for N-polar devices with Si<SUB>x</SUB>N<SUB>y</SUB> passivation, to improve the reproducibility and accuracy in etch depth for the gate recess. A CF<SUB>4</SUB>/O<SUB>2</SUB> plasma based etch, using reactive-ion-etching (RIE) process, has been characterized to study the etch-selectivity between PECVD Si<SUB>x</SUB>N<SUB>y</SUB>, and Al<SUB>2</SUB>O<SUB>3</SUB> deposited by Atomic Layer Deposition (ALD). A high Si<SUB>x</SUB>N<SUB>y</SUB> to Al<SUB>2</SUB>O<SUB>3</SUB> etch-selectivity of 86 was obtained with CF<SUB>4</SUB>/O<SUB>2</SUB> flow rates of 20/2 sccm, and a chamber pressure of 20mT. Lower chamber pressures are desirable for vertical gate recess etch in deep-submicron devices. Hence, the influence of chamber pressure on etch selectivity was characterized. Though the etch selectivity decreased with decreasing chamber pressure, a good selectivity of 37 was obtained even at a 5mT pressure. Based on the above observations, a 1.5 nm Al<SUB>2</SUB>O<SUB>3</SUB> layer was used as an etch-stop in an N-polar GaN MIS-HEMT, to characterize its influence on the device properties. The device was grown by MOCVD on a sapphire substrate and was processed using standard techniques, except for the inclusion of the etch-stop layer. The gate recess was over-etched by 20%, using CF<SUB>4</SUB>/O<SUB>2</SUB> plasma, to completely etch the PECVD Si<SUB>x</SUB>N<SUB>y</SUB> under the gate. Next, the Al<SUB>2</SUB>O<SUB>3</SUB> under the gate region was removed by a wet etch, using AZ-726-MIF developer, followed by Ni/Au/Ni gate deposition. The Al<SUB>2</SUB>O<SUB>3</SUB> etch-stop layer did not cause any noticeable degradation in device properties. The reverse gate to drain leakage was less than 1μA/mm up to a drain bias of -40V, suggesting that no additional leakage paths were created. Pulsed I-V measurements showed no current collapse, indicating good dispersion control in the device. RF power measurements to further validate the etch-stop technology are under progress. In summary, the presented selective etch technology greatly improved the reproducibility of gate recess, without degrading the device properties. This technology would also be valuable for devices employing high-K dielectrics such as Al<SUB>2</SUB>O<SUB>3</SUB> and HfO<SUB>2</SUB> for the gate insulator, with Si<SUB>x</SUB>N<SUB>y</SUB> passivation. |