| Abstract Scope |
Single walled carbon nanotube (SWNT) has the very high sensitivity for the charges because of the around 1 nm size diameter. We fabricated the SWNT transistor with ultra-short gate electrode and observed influence of the single charges trapped in the gate insulator. The device was fabricated as follows. The SWNT was grown by the chemical vapor deposition process on the SiO<SUB>2</SUB> substrate. The bottom side substrate of the SWNT is etched and the SWNT bridges between source and drain electrodes. Then, the SWNT is wrapped around by double-layer of SiN<SUB>x</SUB> of 27 nm over Al<SUB>2</SUB>O<SUB>3</SUB> of 3 nm using atomic layer deposition process (FlexAL, Oxford inst.). The Top gate electrode of 10 nm width is fabricated on the insulator. The drain current is modulated discretely by the applied top gate voltage. The discrete drain current level is observed more than seven levels. When the round-trip top gate voltage is applied, the drain current shows hysteresis characteristic. The width of the hysteresis characteristic also increases discretely with increasing the applied top gate voltage width. Each discrete increase of the hysteresis characteristic width, which is corresponding to the discrete shift of the threshold voltage, shows almost same value. Therefore, the discrete modulation of the drain current is attributed to the influence of the trapped single charge at the interface of the SiN<SUB>x</SUB> and Al<SUB>2</SUB>O<SUB>3</SUB> layers. The top gate electrode width is as narrow as 10 nm and influences at very narrow area. In the narrow area, the trap site is not dense. Therefore, the single charge is trapped there one by one with increasing applied top gate voltage. After the constant top gate voltage is applied, the drain current stays constant value, even though the top gate voltage is returned back to 0 V. This is the memory effect by the single charge trap. At least three levels of the discrete drain current levels show the memory effect. In conclusion, we fabricated the SWNT transistor with ultra-short gate electrode of 10 nm. The device shows the multiple level memory effect by the influence of the trapped single charges. |