We report the first observation of Kirkendall void formation in SiNW contacts and its role in device performance. Understanding the electrical and microstructural aspects of contact formation at nanoscale is essential for the realization of low-resistance metallization suitable for the next-generation of nanowire devices. Traditional thin-film silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) have doped source and drain regions which enables the formation of low-resistance ohmic contacts. Silicon nanowire FETs with in-situ doped source and drain, ion-implanted source and drain, and epitaxially grown doped source and drain have been demonstrated by researchers. The other approach is to use metal silicide contacts to SiNW devices. Silicided source/drain contacts are formed by thermally annealing the deposited contacts to form low-resistance silicide phase in contact with the nanowire. Traditional phase identification techniques such as X-ray diffraction and Auger depth profiling are not effective due to the small volume of the metal-nanowire contact region. So, how do we discover what's actually going on right at the nanowire-metal contact region?
Back-gated FETs with source/drain contacts were formed by depositing Ti/Al/Ti/Au (70 nm / 70 nm / 30 nm / 30 nm) and annealing them at temperatures ranging from 450 °C to 850 °C. In this four-layer design, the first Ti layer in contact with the semiconductor is for the silicidation, the Al layer is placed to reduce the contact resistance of the total metallization stack, and the top two Ti and Au layers are used to protect the Ti/Al layers from oxidation and to facilitate reliable device probing. Scanning transmission electron microscope (STEM) images of the focused ion beam (FIB) cross-sectioned metal/SiNW contact regions of working devices were collected. Chemical analysis and diffraction techniques were used to characterize these cross-sections. As-deposited contacts, and contacts annealed at 550 °C, 750 °C, and 850 °C were studied to identify the extent of metal interdiffusion and reaction with SiNW, and to image the evolution of the metal/NW interface with the change in annealing temperature.
Formation of titanium silicides is observed at the metal/semiconductor interface after the 750 °C anneal. Extensive Si out-diffusion from the nanowire after the 750 °C anneal led to Kirkendall void formation. Annealing at 850 °C led to almost complete out-diffusion of Si from the nanowire core. Devices with 550 °C annealed contacts had linear electrical characteristics; whereas the devices annealed at 750 °C had the best characteristics in terms of linearity, symmetric behavior, and yield. Devices annealed at 850 °C had poor yield, which can be directly attributed to the microstructure of the contact region observed in STEM. We found out that there is a “sweet spot” between forming the right amount of low-resistance phases and destroying the device due to Kirkendall voiding.