| About this Abstract |
| Meeting |
2011 Electronic Materials Conference
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| Symposium
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2011 Electronic Materials Conference
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| Presentation Title |
X1, Gate First In0.53Ga0.47As/Al2O3 MOSFETs with In-Situ Channel Surface Cleaning
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| Author(s) |
Andrew Daniel Carter, Jeremy J.M. Law, William Mitchell, Gregory J. Burek, Brian J. Thibeault, Arthur C. Gossard, Mark J.W. Rodwell |
| On-Site Speaker (Planned) |
Andrew Daniel Carter |
| Abstract Scope |
As scaling of critical dimensions in VLSI becomes difficult, alternatives to silicon are being examined. III-V MOSFETs may provide larger drive currents than silicon at the same equivalent dielectric thickness [1], absent dielectric interfacial defect densities, <I>D<SUB>it</SUB></I>, which degrade subthreshold slope and drive current. While low <I>D<SUB>it</SUB></I> for HfO<SUB>2</SUB> on InGaAs has been reported [2], this result used an arsenic cap to protect the semiconductor surface from oxidation during the transfer between the wafer growth system and the dielectric deposition tool. We have demonstrated <I>D<SUB>it</SUB></I> similar to [2] cleaning the InGaAs surface with hydrogen and trimethylaluminum (TMA) before Al<SUB>2</SUB>O<SUB>3</SUB> deposition [3]. This could eliminate the need for an arsenic cap. Here we report first MOSFET results using such channel surface cleaning techniques. An ~5.5 nm Al<SUB>2</SUB>O<SUB>3</SUB> film was grown in an FlexAL ALD at 300 °C using TMA and deionized water as reactants. We performed an in-situ surface preparation on air exposed samples with iterative cycles of hydrogen plasma and TMA. Hydrogen removes native oxides on the channel surface [4]. Interface quality was measured by capacitance-voltage (CV) on 300 nm, 1E17 cm<SUP>-3</SUP> Si-doped n-type InGaAs surfaces. Gate stack deposition may degrade semiconductor-oxide interface properties [5]. Measurements were done on not annealed and annealed tungsten CV dots to determine damage done by gate metal and SiO<SUB>2</SUB> deposition. Transistor material was grown lattice matched on InP by MBE with the following layer structure: semi-insulating InP substrate, 400 nm undoped InAlAs, 3 nm InAlAs (1E19 cm<SUP>-3</SUP> and 3E19 cm<SUP>-3</SUP> Si doped n-type), and 10 nm undoped InGaAs. Blanket depositions of W/Cr/SiO<SUB>2</SUB>/Cr and subsequent photolithography define a gate stack that is etched by RIE, followed by PECVD SiN<SUB>x</SUB> sidewall deposition and quasi-MEE InAs source-drain regrowth [6]. Finally, devices were metallized using lifted-off Ti/Pd/Au and wet etch mesa isolated. The performance of the depletion mode device (3E19 cm<SUP>-3</SUP> doping) was comparable to the previous enhancement mode result [6] which utilized arsenic capped material to prevent surface oxidation. The enhancement mode device (1E19 cm<SUP>-3</SUP> doping) has a reduced current density and transconductance which are due to large series access resistance underneath the sidewalls. For the depletion mode device, series access resistance to the channel does not explain the poor extrinsic transconductance. Future work will include smaller gate lengths and thinner sidewalls. |
| Proceedings Inclusion? |
Undecided |