| About this Abstract |
| Meeting |
2011 Electronic Materials Conference
|
| Symposium
|
2011 Electronic Materials Conference
|
| Presentation Title |
E6, LATE NEWS: Impact of Mechanical Stress on Stability of Flexible Amorphous Silicon Thin Film Transistors |
| Author(s) |
Melissa Jane Chow, Arash Akhavan Fomani, Maryam Moradi, Arokia Nathan, Gholamreza Chaji, Andrei Sazonov, Rene Lujan, William Wong |
| On-Site Speaker (Planned) |
Melissa Jane Chow |
| Abstract Scope |
The development of functional flexible electronics is essential to enable applications such as conformal medical imagers, wearable health monitoring systems, and flexible light-weight displays. Intensive research on thin-film transistors (TFTs) is being conducted with the goal of producing high-performance devices for improved backplane electronics. However, there are many challenges regarding the performance of devices fabricated at low temperatures that are compatible with flexible plastic substrates. Prior work has reported on the change in TFT characteristics due to mechanical strain, with especially extensive data on the effect of strain on field-effect mobility. While these studies have provided insight into flexible TFT devices, the enhanced functionality of flexible electronics is enabled not only by mechanical compliance but also by long-term electrical stability. This study investigates the effect of gate-bias stress and elastic strain on the long-term stability of flexible low-temperature hydrogenated amorphous silicon (a-Si:H) TFTs.
a-Si:H TFTs were fabricated on flexible polyethylene napthalate (PEN) substrates with a maximum processing temperature of 150°C. Devices had threshold voltages (V<SUB>T</SUB>) of <5V and field-effect mobilities of ~0.7 cm<SUP>2</SUP>/Vs. Uniaxial compressive and tensile stresses of up to approximately 0.2% were applied to the TFTs by bending the devices over several fixtures with concave and convex surfaces of different radii. Devices under different levels of mechanical strain were biased with a constant gate voltage while source/drain current measurements, during and after removal of the gate bias, were taken as a function of time.
It was observed that the rate of threshold voltage shift under d-c gate bias was greater in devices under compressive strain than for devices under a tensile or unstrained state. For short time periods of d-c gate bias (t<1000s), the V<SUB>T</SUB> shift behaviour is mainly due to increased shallow trapping at the semiconductor/dielectric interface as recovery measurements showed a rapid V<SUB>T</SUB> recovery when the gate bias was removed and the device was driven under pulsed conditions. The sub-threshold swing was also found to increase with increasing compressive strain, suggesting the strain also causes an increased rate of defect creation within the semiconductor. Defect creation was more significant in longer-term measurements (t~10,000s), which showed an increase in the sub-threshold swing of over 35% compared to short-term measurements. Recovery of V<SUB>T</SUB> also peaked at final values that were 20% higher than the initial. These results indicate that a combination of the applied mechanical strain and the operating conditions affects the long-term performance of flexible electronic devices. In addition, we will also discuss the effect of device geometry on the electrical stability of flexible a-Si:H devices under strained and unstrained conditions and how device design may be used to minimize the device degradation. |
| Proceedings Inclusion? |
Undecided |