||Iftekhar Chowdhury, MVS Chandrashekhar, Pawel Kaminski, Roman Kozlowski, Paul B Klein, Joshua Caldwell, Kurt Gaskill, Tangali Sudarshan
High voltage SiC devices (~10kV) are of great interest in recent years for smartgrid and other power conversion applications. Recent demonstrations include PiN diodes, Schottky barrier diodes, DMOSFET and implanted VJFET. Epitaxial layers ~100 µm are required to obtain a breakdown voltage ~10 kV. To obtain such large thickness with standard epitaxy processes ~6-7µm/hr, a process time of more than 10 hours is required with the consequent high cost. A new process that overcomes this limitation by adding HCL or using halide precursors has been developed recently. However, the growth of thick epitaxial layers (>50μm) with low doping concentration (<1E14 cm<SUP>-3</SUP>) remains a very difficult task, since the surface morphology usually degrades, exhibiting various morphological defects. In this paper, we will present results on high quality, thick 4H-SiC (0001) 8<SUP>0</SUP> off-axis toward (11-20) that have been grown in a vertical hot-wall chemical vapor deposition (CVD) furnace (temperature 1500<SUP>0</SUP>-1700<SUP>0</SUP>C, pressure 80-300 torr) at a high growth rate using a novel precursor Dichlorosilane, a kinetically favorable halide precursor. RMS roughness in the range of 0.3-0.4 nm with no morphological defects (carrots, triangular defects etc.) has been shown at growth rates 30-100 µm/hr, 5-16 times higher than the conventional speed. The surfaces were specular. Microwave photoconductive decay (µPCD) measurement showed high injection lifetime in the range of 2µs. Site-competition epitaxy was clearly observed over a wide C/Si ratio window (0.9-1.7), with doping concentration <1E14 cm<SUP>-3</SUP>. By maintaining a highly pure growth environment and adjusting the C/Si ratio, we have systematically produced thick high purity semi-insulating (HPSI) epilayers over a C/Si ratio window of 1.3-1.5, a regime we call defect-competition epitaxy. The full width at half maximum (FWHM) obtained using x-ray rocking curves was as narrow as 8arcsec, which indicates the high quality of the epilayers. Micro-Raman spectroscopy showed the 4H polytype uniformity of these HPSI-layers. Resistivity of 1.5x10<SUP>9</SUP> Ohm-cm was determined using transmission line model (TLM) method. Comparison of secondary ion mass spectra (SIMS) between a low doped n- epilayer grown at lower C/Si ratio (~0.9) and a HPSI-epilayer grown at higher C/Si ratio (~1.4) showed no differences in terms of N, Al and B residual impurity concentrations. A correlation of impurity concentration with measured resistivity implied a compensating trap concentration of ~10<SUP>15</SUP> cm<SUP>-3</SUP> present in the HPSI-epilayer. High resolution photo induced transient spectroscopy (HRPITS) analysis identified these traps as Si-vacancy related deep defect centers, with no detectable EH6/7 and Z<SUB>1/2</SUB> levels, consistent with the higher C/Si ratio.