|About this Abstract
||2018 TMS Annual Meeting & Exhibition
||Advanced Microelectronic Packaging, Emerging Interconnection Technology, and Pb-free Solder
||Failure and Material Analysis Challenges in 3D Microelectronic Packages
||Pilin Liu, Kaushik Muthur Srinath, Yan Li, Deepak Goyal
|On-Site Speaker (Planned)
3D microelectronic packaging is essential for improving performance, lowering power, reducing form factor and saving cost for both high-performance computing (HPC) and portable consumer electronics. 2.5D or 3D multi-chip packaging (MCP) allows flexible wafer technologies with different manufacturing process and node to improve yield and reliability. The complex package architecture and small embedded interconnects pose significant challenges for both Fault Isolation (FI) and material analysis. In this presentation, applications of advanced non-destructive FI and imaging methods on identifying the failure locations of fine features embedded in multiple stack packages will be firstly discussed. The presentation will also discuss the combination of using advanced material characterizations including TEM, ToF SIMS, XPS and EBSD on understanding the process or reliability concerns. The cases include micro solder joint quality and interfacial adhesion discussions.
||Planned: Supplemental Proceedings volume