|About this Abstract
||2018 TMS Annual Meeting & Exhibition
||Advanced Microelectronic Packaging, Emerging Interconnection Technology, and Pb-free Solder
||The Effect of Bump Metallurgy on First Level Interconnect Solder Bump Integrity
||Shereen Elhalawaty, George P Vakanas, Jiraporn Seangatith, Prasad Ramanathan, Elah Bozorg-Grayeli, Bharat Penmecha, Pilin Liu, Charles Zhang
|On-Site Speaker (Planned)
Driven by the need for reduced latency and increased bandwidth, reduced bump pitch with reliable solder joint become a critical challenge in advanced microelectronic packaging. Assembling fine bump pitch die to high density organic substrate experienced significant challenges for First Level Interconnect (FLI) joint quality and reliability due to high thermomechanical stress and tapering bump geometry. Consequently, a new bump separation failure mode was observed with very high fail rate post assembly and reliability stress test. Root cause analysis revealed gold migration from the substrate pad to the Ni die bump surface, which formed (Au,Ni)Sn intermetallic (IMC) in a thin continuous dual layer along the die-bump to solder interface. This brittle layer separated from the bulk solder during solidification of the joint. By changing the die bump metallurgy, solder joint integrity is significantly improved. This presentation provides in-depth root cause analysis, highlights the understanding and solutions to this failure mode.
||Planned: Supplemental Proceedings volume