Improvement in the performance of polymeric thin film transistors (TFTs) require a better understanding of how the dielectric interface impacts the formation of the semiconducting polymer interfacial microstructure. The charge carrier mobility of thiophene-based polymers strongly depends on the nature of the molecular orientation at the semiconductor/dielectric interface. The nature of the surface of the dielectric layer has been widely reported to have a significant impact on mobility and overall device behavior but the connection between morphology and electrical performance is not well understood. Furthermore, gate voltage-dependent mobility, variations in threshold voltages, and bias stress have been attributed to dielectric interface effects. To better understand these issues, a dry lamination method utilizing poly(dimethyl siloxane) (PDMS) was used to fabricate polymer-polymer TFTs to avoid any interactions of the dielectric with the solvent used to cast the semiconducting polymer. This dry lamination process enabled the fabrication of a wide variety of semiconducting-dielectric polymeric devices, enabling a direct comparison of how devices performed as a function of the target polymer dielectric and an indirect measure of the interface microstructure as a function of their current-voltage characteristics. Films of two thiophene based semiconducting polymers are formed initially on a known dielectric, octyltrichlorosilane (OTS) modified 150 nm thermal oxide (SiO<SUB>2</SUB>). Using the PDMS lamination process, films are transferred to the target polymer dielectric in their two states, as cast and annealed above the first liquid crystal transition. The carrier mobility in films on OTS/ SiO<SUB>2</SUB> before and after lamination was determined for comparison with results measured on the polymeric dielectrics. These results are then compared with films annealed at the semiconductor’s T<SUB>lc</SUB><SUP>1</SUP> on the target polymer dielectric in order to quantify the effects on the interface microstructure. The electrical characteristics of the TFTs were compared to the bulk morphology determined by grazing incidence wide angle x-ray scattering (GIWAX). TFTs thermally processed, annealing at the semiconductor’s T<SUB>lc</SUB><SUP>1</SUP>, on polystyrene (PS) exhibit a factor of 10 decrease in field effect mobility and an increase in bias stressed threshold voltage, > |1| V, as a function of processing on the polymer dielectric. Observed GIWAX results show an increase in crystallite size and orientation distribution for films annealed on the polymer dielectric but do not give a direct measurement of the interface nor show any change in π-π spacing. This combined data suggests that the semiconducting polymer’s interfacial microstructure has undergone a significant change directly attributed to interactions with the polymeric dielectric.