Due to their unique morphology, large direct bandgap, and excellent crystalline quality, GaN nanowires (NWs) grown by molecular beam epitaxy (MBE) are a promising material for the development of next-generation nanoscale electronic devices. In particular, GaN NW field effect transistors (FETs) have attracted significant interest both for potential device applications and for their usefulness in characterizing NW properties. However, previous GaN NW FETs have relied upon gates that do not make conformal contact to the entire nanowire circumference—at best, the NW has been sandwiched between a top and a bottom gate. This approach has generally led to inefficient gating. In addition, the asymmetric gate geometry of such devices makes it difficult to accurately extract NW carrier concentration from measured threshold voltages. In this report, we demonstrate novel n-type GaN NW metal oxide semiconductor FETs (MOSFETs) with symmetric, fully conformal cylindrical gates. After the MBE NW growth process, the as-grown NWs were conformally coated with approximately 43 nm of Al<SUB>2</SUB>O<SUB>3</SUB> (<I>k</I> ~7.6) and 35 nm of W via atomic layer deposition (ALD). The coated NWs were then harvested from the growth substrate and aligned by dielectrophoresis across electrodes on the device substrate. After masking the central gate region of each NW with photoresist, the W and Al<SUB>2</SUB>O<SUB>3</SUB> layers were removed from the two end regions (source and drain) of the NW by tungsten etchant and 10:1 buffered oxide etchant (BOE). Finally, ohmic source and drain contacts and a contact to the W/Al<SUB>2</SUB>O<SUB>3</SUB> gate were deposited. The completed surround-gate MOSFETs operated as n-channel depletion mode devices, with each device containing a single NW. Threshold gate voltages were typically between -5 and -12 V, with subthreshold gate leakage current on the order of 1 pA or less. On/off current ratios as high as 10<SUP>9</SUP> were achieved with a drain-source bias of 5 to 6 V. Maximum transconductances exceeded 10 μS. These characteristics compare favorably with the best GaN NW-based FETs that have been previously demonstrated. By taking advantage of the radial symmetry of the gate and applying simple electrostatic analysis by use of Gauss’ Law, the NW carrier concentrations were estimated from the threshold voltages to be between 4 × 10<SUP>17</SUP> and 9 × 10<SUP>17</SUP> cm<SUP>-3</SUP>. Although these devices had excellent pinchoff characteristics, the NW MOSFETs also showed significant memory effects in gating. Hysteresis occurred during bi-directional gate voltage sweeps. In addition, threshold voltages sometimes drifted during repeated gate bias, resulting in uncertainty in the calculation of carrier concentration. These effects are most likely due to charge trapping at the NW/oxide interface or within the ALD Al<SUB>2</SUB>O<SUB>3</SUB> layer. The nature of these charge traps is the subject of ongoing investigation.