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Meeting Materials Science & Technology 2019
Symposium Advanced Microelectronic Packaging, Emerging Interconnection Technology, and Pb-free Solder
Presentation Title Effect of Thermal Annealing on Structural Integrity of Cu-filled-through Si Via (TSV)
Author(s) Dipali Shivaji Sonawane, Praveen Kumar
On-Site Speaker (Planned) Dipali Shivaji Sonawane
Abstract Scope Cu-filled through-silicon vias (TSV) are used as interconnects while stacking multiple dies in a 3-D microelectronic package. Large difference in thermal expansion coefficients of Cu and Si generates significantly large thermal stresses during thermal excursions, e.g., during post-fabrication annealing or in-service, that raises serious thermo-mechanical reliability issues. Herein, annealing experiments were performed on Cu-filled-TSVs over the temperature range of 250 to 650 C. Extrusion of Cu relative to Si and nucleation of micro-cracks in Si in vicinity of Cu pillars were observed. Besides crack propagation during subsequent annealing cycles, cracks also grew during room temperature aging, thereby substantiating delayed fracture in Si. This is the very first-time slow crack growth has been observed in Cu-filled-TSV. It can be attributed to the oxidation of Si at the crack tip and residual thermal stresses. In addition, extended finite element analysis was performed to gain insights into the observed experimental results.
Proceedings Inclusion? Definite: At-meeting proceedings


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