|About this Abstract
||2018 TMS Annual Meeting & Exhibition
||Advanced Microelectronic Packaging, Emerging Interconnection Technology, and Pb-free Solder
||Advances in Copper Electroplating for IC Substrate Packaging Applications
||Kousik Ganesan, Amaneh Tasooji, Rahul Manepalli
|On-Site Speaker (Planned)
Interconnect circuitry in IC substrate packages is comprised of stacked micro via’s and fine line patterns. Electrodeposition of copper is utilized to establish the desired circuitry. Electrodeposition of copper in such applications holds certain unique challenges compared to the traditional dual damascene applications. For example, IC substrate packages require low cost, void free complete fill along with a deposition of uniform copper film in fine line spaces (FLS) without the addition of a planarization process. We demonstrate a reverse pulse plating methodology to influence gap fill behavior and achieve uniform plating for these IC substrate applications. Systematic studies of “optimal” pulse and pulse-reverse waveforms are provided to tweak gap fill behavior all in while ensuring uniform plating in fine line spaces. Specifically insights into the physics of via fill process is presented with challenging via geometry / shapes generated through LASER drill process to show “smart” control of deposition rates.
||Planned: Supplemental Proceedings volume